Tin perovskite transistors and complementary circuits based on A-site cation engineering
Tin halide perovskites possess the chemical formula of ASnX 3., where A is a single-valent Cation, and X is a monovalent anion. These semiconducting materials could be used to create transistors of the p-type at a low cost and temperature and are possibly integrated with n-type oxide-based transistors to make complementary circuits. However, the materials are plagued by common crystallization control and high defect density, leading to low-quality device performance. Here, we show that pure-tin perovskite thin-film transistors can be created using triple A cations of caesium-formamidinium-phenethylammonium. The approach leads to high-quality cascaded tin perovskite channel films with low-defect, phase-pure perovskite/dielectric interfaces. Thin-film transistors that have been optimized show holes with mobilities that exceed 70cm 2. V 1 s 1 and current ratios on/off that exceed 10 8 are comparable with the commercial low-temperature polysilicon transistors. The transistors are constructed using a solution-processing method at temperatures not exceeding 100 degrees Celsius. We also incorporate the devices with the n-type metal oxide transistors to make complementary inverters with voltage increases of 370, as well as NAND and NOR logic gates with rail-to-rail switching capabilities.
The commercialization and development of high-performance field-effect n-type metal oxide transistors have surpassed their p-type equivalents 1. Tin (Sn 2+) Halide Perovskites, like cesium triiodide (CsSnI 3) and methylammonium triiodide (MASnI 3), are semiconductors of the p-type with high hole mobility (several thousands of square centimeters of square centimeters for each volt second) and outstanding processing capabilities through low-cost, scalable, and cost-effective film deposition techniques 3,5,6,7 and 8. Their dispersive valence band maxima and their small hole mass of the carrier (comparable to silicon) give them excellent intrinsic transport properties. As a result, tin perovskites are promising semiconductors for the development of high-performance p-channel transistors, which could be used with n-channel metal oxide transistors to create noise-immune and low-power-consumption complementary-metal-oxide-semiconductor-like electronics9,10,11.
The creation of high-performance tin perovskite transistors (TFTs) requires the production of top-quality tin perovskite semiconductor films. However, perovskites generally exhibit rapid crystallization of the film, which can lead to damaged films and poor device efficiency 12.13. Engineering with B- and X-sites (Pb and Br/Cl allocation) can cause slowdowns in Sn-I perovskite crystalline growth, resulting in homogeneous films with refined grains and minimal imperfections 14.15. Perovskite TFTs produced using this technique can offer impressive electrical performance and achieve high fields-of-effect (mFE) of 50cm2 V-1/s-1. However, heavy Pb and br/Cl with muscular ionic strength raise questions regarding Pb poisoning and increase Frohlich interactions between charge carriers and the electric fields created by phonons, restricting charge carrier mobility at ambient temperatures. Three.
Initially, B-/X-site components may benefit from large hole mobility due to the powerful Sn5 s-I5 p coupling near the valence-band maximum and the weak Frohlich interplay 3. The A-site cation exerts a less direct impact on the edge of the band. However, it can assist in crystallization, alter the threshold factor aid, stabilize the structure and entropic chemistry, and, in turn, improve the properties of perovskite 16-17. Previous attempts, such as mixing A cations to create core-shell structures and creating more efficient bulky organic spacers, have enhanced the TFT’s performance; however, the maximum mFE is less than the 25cm2 of V-1 (refs. 6,7,11). In this article, we show that the A cations of cesium-formamidinium-phenethylammonium (CsFAPEA) can be used to create high-quality cascaded pure-Sn-channel films and a low-defect phase-pure perovskite/dielectric interface. The TFTs that are optimized have holes with mobility of more than 70cm2 V-1/s-1 as well as an Ion/Ioff ratio (Ion/Ioff) over 108, which is comparable to the commercial low-temperature polysilicon (LTPS) performance of the device.
A-cation-engineered Sn TFTs
The Sn perovskite thin films (~30 nm thickness) with various A-cation mixtures were formed on silica dielectric (SiO 2; 100 Nm thickness) substrates prepared from various precursors using spin coating then followed by the gold drain electrode and source extrusion, which resulted in top-contact TFTs with the bottom gate (Fig. 1a). The various precursors that mostly contain desirable A-cation compositions and tin(II) Iodide (SnI 2) were prepared using an instrument box. All the details about preparation are described in the methods. We make use of the names FA, FAPEA, and CsFAPEA to refer to all perovskite-based compounds that act as semiconducting layers within TFTs that have optimized performance according to the kind. Pure FA devices exhibit conductor behaviors with no field effect as well as on/off. Off off (Supplementary Fig. off (Supplementary Figure. 1a). These phenomena are a result of the extensive background hole density that occurs in the 3D (3D) Sn perovskites because of the low energy of formation for Sn-vacancy defects 18.19. Then, we employed PEA cations, which could modify the crystallization in FASnI 3 perovskite and reduce the number of defects 20-21. It is also evident that the FAPEA TFTs (made by utilizing an optimal ratio of molars between FA and PEA = 7:2) clearly show field-effect modulation, with an average mFE of 14 cm2 V-1 s-1 and Ion/Ioff values of 2.5 x the value of 107 (Supplementary Figure. 1a). To investigate the possibility of better and more competitive TFT performances, we used in the 3rd Cs cation, which is a substitute for the partial FA Cations.
Fig. 1: Electrical properties of TFT.
A structural scheme for the Sn perovskite TFT. The arrow shows the transport pathway of charge carriers. Ion/Ioff, b, and mFE of TFTs based upon channels made from mixed precursors having various Cs molar ratios The x in (CsxFA1-x)7PEA2. These error bars were calculated based on ten devices per type, and the data are reported as mean + standard deviation. C, d transfer ( c) and output ( d) characteristics of optimal TFTs (Cs ratio equals 10 mol 10%). The I G within c is the leakage current in the gate. The IDS VGS data from the forward scan are displayed in the blue line, corresponding with the right-hand y direction. VDS = -40 V. Channel width/length = 1,000 mm/200 mm. Supplementary Fig. 4 shows the electrode’s geometry. E-transfer characteristics of 50 distinct CsFAPEA TFTs made from ten batches. The figure shows M F data. F (f), Representative m FE values of perovskite TFTs based on various channel films. Low-temperature Polysilicon Level (mFE 70cm2 V-1, s-1, Ion/Ioff107).
Surprisingly, the triple-cation-engineered TFTs show notably boosted performance. Ten mol% Cs substitution delivers the optimal improvement, including a fivefold higher mFE and tenfold higher Ion/Ioff compared with those of pristine FAPEA TFTs (Fig. 1b). A lower or higher Cs ratio reduces mFE and Ion/Ioff, resulting in a noticeable dual-sweep hysteresis (Supplementary Figure. 1b). The typical p-channel transfer characteristics of an optimized CsFAPEA TFT (denoting (CsxFA1-x)PEA2Sn8I25, x = 10%) are shown in Fig. 1c. The TFT has a very high mFE that is 72 cm2 V-1 as well as an Ion/Ioff values of 2.6 to 108, with a small dual-sweep hysteresis, and a subthre of swing (SS) that is 0.5 V dec-1 (discussed in the following section). Supplementary Fig. 2 illustrates the graph of m FE against gate voltage. The output characteristics for the CsFAPEA TFT demonstrate excellent linearity at low drain-source voltages ( V DS) and saturation of current when the voltage is at the highest levels of V the drain-source voltage (Fig. 1d), which suggests low injection barriers for charge carriers and an ohmic connection between the perovskite channel as well as gold electrodes. A fairly low contact resistance of about one kO centimeter was determined using the transmission-line technique 22 (Supplementary Figure. 3). The TFTs also have a high degree of reproducibility and a mean mFE value of 67.6 +/- 3.6 cm2 V-1 s-1 derived from 50 devices over ten different batches (Fig. 1.e.) which had an average Ion/Ioff of (1.8 + 0.3) (x 108) with an SS was 0.8 + 0.2 V as well as a threshold VTH (VTH) that is 20.4 + 2.9 V (statistics are defined as mean + the standard deviation). Such electrical parameters are superior to those of the devices based on other perovskite semiconductors6,7,9,11,14,15,19,23,24,25,26,27, and comparable with the commercial LTPS level (Fig. 1f).
Film structure and morphology
We then attempted to discover the reason behind the remarkable TFT performance. The morphologies of different pure-Sn films are illustrated in Fig. 2a. The original 3D FA film shows poor film coverage, with many gaps and distinct grain boundary that is normal due to the speedy crystallization process. That is the rapid growth of crystals prior to nucleation being complete 28. The grain boundary is high in defect-rich regions, resulting in the highly doped nature of the pure FA films, which have low charge transport properties. PEA substitution dramatically improved the film’s morphology with much greater coverage, with just a few empty spaces. Also, it was observed that the grains tend to join together, resulting in the film as a molten state with no apparent boundaries. This is similar to previously observed results from improved Sn Perovskite film 12-15. The control of crystallization is crucial to the production of top-quality pure-Sn perovskite film 12. The slower crystallization process could explain the enhanced FAPEA film morphology because the massive PEA Cations in the precursor block the speedy reactions between perovskite elements 29. However, indeed, the FAPEA film is still uneven with high roughness and voids, which indicates that the control of rapid crystallization is not quite enough to be sufficient. By additional Cs substitutes, improved CsFAPEA film displays smooth morphology and full coverage. Its roughness ( R q) for the CsFAPEA film is just 1.37 millimeters (Fig. 2b), approximately 50% of the FAPEA film. The smooth and pinhole-free morphology three-cation CsFAPEA semiconducting material can improve the transport of charge carriers in devices, as well as improve the TFT quality and uniformity.